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<title>MTB CAT1 Peripheral driver library: cy_stc_pra_system_config_t Struct Reference</title>
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<div class="header">
  <div class="summary">
<a href="#pub-attribs">Data Fields</a>  </div>
  <div class="headertitle">
<div class="title">cy_stc_pra_system_config_t Struct Reference<div class="ingroups"><a class="el" href="group__group__pra.html">PRA          (Protected Register Access)</a> &raquo; <a class="el" href="group__group__pra__stc.html">Data Structures</a></div></div>  </div>
</div><!--header-->
<div class="contents">
<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<div class="textblock"><p>System configuration structure. </p>
</div><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:ad8bd2e696d81a75161f4c6a105e46b3b"><td class="memItemLeft" align="right" valign="top"><a id="ad8bd2e696d81a75161f4c6a105e46b3b"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#ad8bd2e696d81a75161f4c6a105e46b3b">powerEnable</a></td></tr>
<tr class="memdesc:ad8bd2e696d81a75161f4c6a105e46b3b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Power is enabled or disabled. <br /></td></tr>
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bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a8882b3dda29566831ac7907d71fb23bc">ldoEnable</a></td></tr>
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bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#ac0b41593a40ab38971c76c181bc2e4a2">pmicEnable</a></td></tr>
<tr class="memdesc:ac0b41593a40ab38971c76c181bc2e4a2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Power using external PMIC output. <br /></td></tr>
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bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a76b55db0d1d075fca71d1c8b9211bd86">vBackupVDDDEnable</a></td></tr>
<tr class="memdesc:a76b55db0d1d075fca71d1c8b9211bd86"><td class="mdescLeft">&#160;</td><td class="mdescRight">vBackup source using VDD or Direct supply <br /></td></tr>
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bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#afb72378080a3385a917c9644a4e26e3e">ulpEnable</a></td></tr>
<tr class="memdesc:afb72378080a3385a917c9644a4e26e3e"><td class="mdescLeft">&#160;</td><td class="mdescRight">System Active Power mode is ULP. <br /></td></tr>
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bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#af3b74dfb43417476a2c21c0c7525273d">ecoEnable</a></td></tr>
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bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#aea5ecb63a8fcce3be115af0734376c8a">iloEnable</a></td></tr>
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bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#aea04aa5dbaa0bede943ade96e68b389d">wcoEnable</a></td></tr>
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bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a45b41dd4b18f6609ad4ecc348f49f5d5">fllEnable</a></td></tr>
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bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a175808966048c1ee9657ccd7cd3e886d">pll0Enable</a></td></tr>
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bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a3cf9eaab5089a4bae71d2681966d0d84">pll1Enable</a></td></tr>
<tr class="memdesc:a3cf9eaab5089a4bae71d2681966d0d84"><td class="mdescLeft">&#160;</td><td class="mdescRight">PLL1 Enable. <br /></td></tr>
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bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#ab7a9778a9d5ce4a30191826baa7e0ee6">path0Enable</a></td></tr>
<tr class="memdesc:ab7a9778a9d5ce4a30191826baa7e0ee6"><td class="mdescLeft">&#160;</td><td class="mdescRight">PATH_MUX0 Enable. <br /></td></tr>
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bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a8db19ef8fa9f1649ed51aac89bbc4b92">path1Enable</a></td></tr>
<tr class="memdesc:a8db19ef8fa9f1649ed51aac89bbc4b92"><td class="mdescLeft">&#160;</td><td class="mdescRight">PATH_MUX1 Enable. <br /></td></tr>
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bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a38af71d7866bc5d9f6260978fd22c4fd">path2Enable</a></td></tr>
<tr class="memdesc:a38af71d7866bc5d9f6260978fd22c4fd"><td class="mdescLeft">&#160;</td><td class="mdescRight">PATH_MUX2 Enable. <br /></td></tr>
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bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#ae9a7204e6f8a003a9193420ac2d0ca43">path3Enable</a></td></tr>
<tr class="memdesc:ae9a7204e6f8a003a9193420ac2d0ca43"><td class="mdescLeft">&#160;</td><td class="mdescRight">PATH_MUX3 Enable. <br /></td></tr>
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<tr class="memitem:a84509cea0241bd05c6a3e1b8ad3980df"><td class="memItemLeft" align="right" valign="top"><a id="a84509cea0241bd05c6a3e1b8ad3980df"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a84509cea0241bd05c6a3e1b8ad3980df">path4Enable</a></td></tr>
<tr class="memdesc:a84509cea0241bd05c6a3e1b8ad3980df"><td class="mdescLeft">&#160;</td><td class="mdescRight">PATH_MUX4 Enable. <br /></td></tr>
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<tr class="memitem:a82abf3f1f4ca5fa3c0c43a2771bdc9e4"><td class="memItemLeft" align="right" valign="top"><a id="a82abf3f1f4ca5fa3c0c43a2771bdc9e4"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a82abf3f1f4ca5fa3c0c43a2771bdc9e4">path5Enable</a></td></tr>
<tr class="memdesc:a82abf3f1f4ca5fa3c0c43a2771bdc9e4"><td class="mdescLeft">&#160;</td><td class="mdescRight">PATH_MUX5 Enable. <br /></td></tr>
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<tr class="memitem:a0959413ddce282ed12ac4d71a7ad07a0"><td class="memItemLeft" align="right" valign="top"><a id="a0959413ddce282ed12ac4d71a7ad07a0"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a0959413ddce282ed12ac4d71a7ad07a0">clkFastEnable</a></td></tr>
<tr class="memdesc:a0959413ddce282ed12ac4d71a7ad07a0"><td class="mdescLeft">&#160;</td><td class="mdescRight">CLKFAST Enable. <br /></td></tr>
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<tr class="memitem:a90fb8235131fba7431e36ca71e4fb823"><td class="memItemLeft" align="right" valign="top"><a id="a90fb8235131fba7431e36ca71e4fb823"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a90fb8235131fba7431e36ca71e4fb823">clkPeriEnable</a></td></tr>
<tr class="memdesc:a90fb8235131fba7431e36ca71e4fb823"><td class="mdescLeft">&#160;</td><td class="mdescRight">CLKPERI Enable. <br /></td></tr>
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<tr class="memitem:a30db8858fe85baae2d48e8d3d66e344b"><td class="memItemLeft" align="right" valign="top"><a id="a30db8858fe85baae2d48e8d3d66e344b"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a30db8858fe85baae2d48e8d3d66e344b">clkSlowEnable</a></td></tr>
<tr class="memdesc:a30db8858fe85baae2d48e8d3d66e344b"><td class="mdescLeft">&#160;</td><td class="mdescRight">CLKSLOW Enable. <br /></td></tr>
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<tr class="memitem:a3862f0c159e4c9f2ba82ac15cbf54bb2"><td class="memItemLeft" align="right" valign="top"><a id="a3862f0c159e4c9f2ba82ac15cbf54bb2"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a3862f0c159e4c9f2ba82ac15cbf54bb2">clkHF0Enable</a></td></tr>
<tr class="memdesc:a3862f0c159e4c9f2ba82ac15cbf54bb2"><td class="mdescLeft">&#160;</td><td class="mdescRight">CLKHF0 Enable. <br /></td></tr>
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<tr class="memitem:aaa71c95c74de22c7646718df7ef712a7"><td class="memItemLeft" align="right" valign="top"><a id="aaa71c95c74de22c7646718df7ef712a7"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#aaa71c95c74de22c7646718df7ef712a7">clkHF1Enable</a></td></tr>
<tr class="memdesc:aaa71c95c74de22c7646718df7ef712a7"><td class="mdescLeft">&#160;</td><td class="mdescRight">CLKHF1 Enable. <br /></td></tr>
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<tr class="memitem:a3fbac8dafc91771503270b8760efd443"><td class="memItemLeft" align="right" valign="top"><a id="a3fbac8dafc91771503270b8760efd443"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a3fbac8dafc91771503270b8760efd443">clkHF2Enable</a></td></tr>
<tr class="memdesc:a3fbac8dafc91771503270b8760efd443"><td class="mdescLeft">&#160;</td><td class="mdescRight">CLKHF2 Enable. <br /></td></tr>
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bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a2f3d5778daffe24eaddafc81e96f1e4b">clkHF3Enable</a></td></tr>
<tr class="memdesc:a2f3d5778daffe24eaddafc81e96f1e4b"><td class="mdescLeft">&#160;</td><td class="mdescRight">CLKHF3 Enable. <br /></td></tr>
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bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a2ff30be2f024d55c489e99b1b6fc4032">clkHF4Enable</a></td></tr>
<tr class="memdesc:a2ff30be2f024d55c489e99b1b6fc4032"><td class="mdescLeft">&#160;</td><td class="mdescRight">CLKHF4 Enable. <br /></td></tr>
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bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#adf4c43fa5d1146dcb82b4b4fd878f8d3">clkHF5Enable</a></td></tr>
<tr class="memdesc:adf4c43fa5d1146dcb82b4b4fd878f8d3"><td class="mdescLeft">&#160;</td><td class="mdescRight">CLKHF5 Enable. <br /></td></tr>
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<tr class="memitem:ae1d40573a1ddc4802896a06e03bbfa33"><td class="memItemLeft" align="right" valign="top"><a id="ae1d40573a1ddc4802896a06e03bbfa33"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#ae1d40573a1ddc4802896a06e03bbfa33">clkPumpEnable</a></td></tr>
<tr class="memdesc:ae1d40573a1ddc4802896a06e03bbfa33"><td class="mdescLeft">&#160;</td><td class="mdescRight">CLKPUMP Enable. <br /></td></tr>
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<tr class="memitem:aaaef4ee4809207c941b563084a27f744"><td class="memItemLeft" align="right" valign="top"><a id="aaaef4ee4809207c941b563084a27f744"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#aaaef4ee4809207c941b563084a27f744">clkLFEnable</a></td></tr>
<tr class="memdesc:aaaef4ee4809207c941b563084a27f744"><td class="mdescLeft">&#160;</td><td class="mdescRight">CLKLF Enable. <br /></td></tr>
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<tr class="memitem:ab38f5329598b357aa383e1bb24eae84c"><td class="memItemLeft" align="right" valign="top"><a id="ab38f5329598b357aa383e1bb24eae84c"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#ab38f5329598b357aa383e1bb24eae84c">clkBakEnable</a></td></tr>
<tr class="memdesc:ab38f5329598b357aa383e1bb24eae84c"><td class="mdescLeft">&#160;</td><td class="mdescRight">CLKBAK Enable. <br /></td></tr>
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<tr class="memitem:a02a64957b1187888d2f62d1cbc686def"><td class="memItemLeft" align="right" valign="top"><a id="a02a64957b1187888d2f62d1cbc686def"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a02a64957b1187888d2f62d1cbc686def">clkTimerEnable</a></td></tr>
<tr class="memdesc:a02a64957b1187888d2f62d1cbc686def"><td class="mdescLeft">&#160;</td><td class="mdescRight">CLKTIMER Enable. <br /></td></tr>
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<tr class="memitem:a51313911743e88921f2d7188a0e85114"><td class="memItemLeft" align="right" valign="top"><a id="a51313911743e88921f2d7188a0e85114"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a51313911743e88921f2d7188a0e85114">clkAltSysTickEnable</a></td></tr>
<tr class="memdesc:a51313911743e88921f2d7188a0e85114"><td class="mdescLeft">&#160;</td><td class="mdescRight">CLKALTSYSTICK Enable. <br /></td></tr>
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<tr class="memitem:aa45ddad91cfcee24d451cb6164eac2b0"><td class="memItemLeft" align="right" valign="top"><a id="aa45ddad91cfcee24d451cb6164eac2b0"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#aa45ddad91cfcee24d451cb6164eac2b0">piloEnable</a></td></tr>
<tr class="memdesc:aa45ddad91cfcee24d451cb6164eac2b0"><td class="mdescLeft">&#160;</td><td class="mdescRight">PILO Enable. <br /></td></tr>
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<tr class="memitem:a48fc2bc7301fa24aea3283995bd6af0c"><td class="memItemLeft" align="right" valign="top"><a id="a48fc2bc7301fa24aea3283995bd6af0c"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a48fc2bc7301fa24aea3283995bd6af0c">clkAltHfEnable</a></td></tr>
<tr class="memdesc:a48fc2bc7301fa24aea3283995bd6af0c"><td class="mdescLeft">&#160;</td><td class="mdescRight">BLE ECO Clock Enable. <br /></td></tr>
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<tr class="memitem:a83dd0313cc72422db9ae53f446992b4e"><td class="memItemLeft" align="right" valign="top"><a id="a83dd0313cc72422db9ae53f446992b4e"></a>
<a class="el" href="group__group__syspm__data__enumerates.html#gaef8ba4a0ee827abcaaf62f950e69496e">cy_en_syspm_ldo_voltage_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a83dd0313cc72422db9ae53f446992b4e">ldoVoltage</a></td></tr>
<tr class="memdesc:a83dd0313cc72422db9ae53f446992b4e"><td class="mdescLeft">&#160;</td><td class="mdescRight">LDO Voltage (LP or ULP) <br /></td></tr>
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<tr class="memitem:a449bd7d8fe6e4bf2f1e353ce2eff25bd"><td class="memItemLeft" align="right" valign="top"><a id="a449bd7d8fe6e4bf2f1e353ce2eff25bd"></a>
<a class="el" href="group__group__syspm__data__enumerates.html#ga3917bcfb5a7b4151ec1b0fcd95c37d5a">cy_en_syspm_buck_voltage1_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a449bd7d8fe6e4bf2f1e353ce2eff25bd">buckVoltage</a></td></tr>
<tr class="memdesc:a449bd7d8fe6e4bf2f1e353ce2eff25bd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Buck Voltage. <br /></td></tr>
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<tr class="memitem:ab87e31ad976a8aa36fbcb142812088a1"><td class="memItemLeft" align="right" valign="top"><a id="ab87e31ad976a8aa36fbcb142812088a1"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#ab87e31ad976a8aa36fbcb142812088a1">pwrCurrentModeMin</a></td></tr>
<tr class="memdesc:ab87e31ad976a8aa36fbcb142812088a1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Minimum core regulator current mode. <br /></td></tr>
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<tr class="memitem:a25918adb4a58c0e81f0b2ba39e63b010"><td class="memItemLeft" align="right" valign="top"><a id="a25918adb4a58c0e81f0b2ba39e63b010"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a25918adb4a58c0e81f0b2ba39e63b010">ecoFreqHz</a></td></tr>
<tr class="memdesc:a25918adb4a58c0e81f0b2ba39e63b010"><td class="mdescLeft">&#160;</td><td class="mdescRight">ECO Frequency in Hz. <br /></td></tr>
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<tr class="memitem:a8f628f024f9695b15613f175c9318da9"><td class="memItemLeft" align="right" valign="top"><a id="a8f628f024f9695b15613f175c9318da9"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a8f628f024f9695b15613f175c9318da9">ecoLoad</a></td></tr>
<tr class="memdesc:a8f628f024f9695b15613f175c9318da9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Parallel Load Capacitance (pF) <br /></td></tr>
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<tr class="memitem:aff6db3637fa0d06ac7f7877730aac7d0"><td class="memItemLeft" align="right" valign="top"><a id="aff6db3637fa0d06ac7f7877730aac7d0"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#aff6db3637fa0d06ac7f7877730aac7d0">ecoEsr</a></td></tr>
<tr class="memdesc:aff6db3637fa0d06ac7f7877730aac7d0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Equivalent series resistance (ohm) <br /></td></tr>
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<tr class="memitem:a1027534c1b3e80c5bec3fa257aa8d4e3"><td class="memItemLeft" align="right" valign="top"><a id="a1027534c1b3e80c5bec3fa257aa8d4e3"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a1027534c1b3e80c5bec3fa257aa8d4e3">ecoDriveLevel</a></td></tr>
<tr class="memdesc:a1027534c1b3e80c5bec3fa257aa8d4e3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Drive Level (uW) <br /></td></tr>
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<tr class="memitem:a2eff229c12795b811978d92c07f018d9"><td class="memItemLeft" align="right" valign="top"><a id="a2eff229c12795b811978d92c07f018d9"></a>
<a class="el" href="struct_g_p_i_o___p_r_t___type.html">GPIO_PRT_Type</a> *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a2eff229c12795b811978d92c07f018d9">ecoInPort</a></td></tr>
<tr class="memdesc:a2eff229c12795b811978d92c07f018d9"><td class="mdescLeft">&#160;</td><td class="mdescRight">ECO input port. <br /></td></tr>
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<tr class="memitem:ae44591912397b29081a16b882d1dd7ae"><td class="memItemLeft" align="right" valign="top"><a id="ae44591912397b29081a16b882d1dd7ae"></a>
<a class="el" href="struct_g_p_i_o___p_r_t___type.html">GPIO_PRT_Type</a> *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#ae44591912397b29081a16b882d1dd7ae">ecoOutPort</a></td></tr>
<tr class="memdesc:ae44591912397b29081a16b882d1dd7ae"><td class="mdescLeft">&#160;</td><td class="mdescRight">ECO output port. <br /></td></tr>
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<tr class="memitem:aeb7d4d558ae78f9ca6e6395c7e2e28c3"><td class="memItemLeft" align="right" valign="top"><a id="aeb7d4d558ae78f9ca6e6395c7e2e28c3"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#aeb7d4d558ae78f9ca6e6395c7e2e28c3">ecoInPinNum</a></td></tr>
<tr class="memdesc:aeb7d4d558ae78f9ca6e6395c7e2e28c3"><td class="mdescLeft">&#160;</td><td class="mdescRight">ECO input pin number. <br /></td></tr>
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<tr class="memitem:a28d283aa2e80ca93a1d2ba2b04c3edb3"><td class="memItemLeft" align="right" valign="top"><a id="a28d283aa2e80ca93a1d2ba2b04c3edb3"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a28d283aa2e80ca93a1d2ba2b04c3edb3">ecoOutPinNum</a></td></tr>
<tr class="memdesc:a28d283aa2e80ca93a1d2ba2b04c3edb3"><td class="mdescLeft">&#160;</td><td class="mdescRight">ECO output pin number. <br /></td></tr>
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<tr class="memitem:a92523a2827d7627e77c1566566951cd9"><td class="memItemLeft" align="right" valign="top"><a id="a92523a2827d7627e77c1566566951cd9"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a92523a2827d7627e77c1566566951cd9">extClkFreqHz</a></td></tr>
<tr class="memdesc:a92523a2827d7627e77c1566566951cd9"><td class="mdescLeft">&#160;</td><td class="mdescRight">External clock frequency in Hz. <br /></td></tr>
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<tr class="memitem:ac83be3d598cd832ee897b72b65dfc02f"><td class="memItemLeft" align="right" valign="top"><a id="ac83be3d598cd832ee897b72b65dfc02f"></a>
<a class="el" href="struct_g_p_i_o___p_r_t___type.html">GPIO_PRT_Type</a> *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#ac83be3d598cd832ee897b72b65dfc02f">extClkPort</a></td></tr>
<tr class="memdesc:ac83be3d598cd832ee897b72b65dfc02f"><td class="mdescLeft">&#160;</td><td class="mdescRight">External connection port. <br /></td></tr>
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<tr class="memitem:a6c424c0cface08a9d56e42993d40004d"><td class="memItemLeft" align="right" valign="top"><a id="a6c424c0cface08a9d56e42993d40004d"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a6c424c0cface08a9d56e42993d40004d">extClkPinNum</a></td></tr>
<tr class="memdesc:a6c424c0cface08a9d56e42993d40004d"><td class="mdescLeft">&#160;</td><td class="mdescRight">External connection pin. <br /></td></tr>
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<tr class="memitem:aa232453c0b9307951262b56113a1f0aa"><td class="memItemLeft" align="right" valign="top"><a id="aa232453c0b9307951262b56113a1f0aa"></a>
<a class="el" href="group__group__gpio__enums.html#ga678dc02e490d04efdcfec78648899ce4">en_hsiom_sel_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#aa232453c0b9307951262b56113a1f0aa">extClkHsiom</a></td></tr>
<tr class="memdesc:aa232453c0b9307951262b56113a1f0aa"><td class="mdescLeft">&#160;</td><td class="mdescRight">IO mux value. <br /></td></tr>
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<tr class="memitem:a6b28c399d82443b81de21d953455ce62"><td class="memItemLeft" align="right" valign="top"><a id="a6b28c399d82443b81de21d953455ce62"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a6b28c399d82443b81de21d953455ce62">iloHibernateON</a></td></tr>
<tr class="memdesc:a6b28c399d82443b81de21d953455ce62"><td class="mdescLeft">&#160;</td><td class="mdescRight">Run in Hibernate Mode. <br /></td></tr>
<tr class="separator:a6b28c399d82443b81de21d953455ce62"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2f3c8b87509eec88a8d1ff107b04b0af"><td class="memItemLeft" align="right" valign="top"><a id="a2f3c8b87509eec88a8d1ff107b04b0af"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a2f3c8b87509eec88a8d1ff107b04b0af">bypassEnable</a></td></tr>
<tr class="memdesc:a2f3c8b87509eec88a8d1ff107b04b0af"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clock port bypass to External sine wave or to normal crystal. <br /></td></tr>
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<tr class="memitem:a23364ee6a0f0d6ea09fe0c48422ee412"><td class="memItemLeft" align="right" valign="top"><a id="a23364ee6a0f0d6ea09fe0c48422ee412"></a>
<a class="el" href="struct_g_p_i_o___p_r_t___type.html">GPIO_PRT_Type</a> *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a23364ee6a0f0d6ea09fe0c48422ee412">wcoInPort</a></td></tr>
<tr class="memdesc:a23364ee6a0f0d6ea09fe0c48422ee412"><td class="mdescLeft">&#160;</td><td class="mdescRight">WCO Input port. <br /></td></tr>
<tr class="separator:a23364ee6a0f0d6ea09fe0c48422ee412"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4cd08dbd4b55e3b80e34ed78694d1399"><td class="memItemLeft" align="right" valign="top"><a id="a4cd08dbd4b55e3b80e34ed78694d1399"></a>
<a class="el" href="struct_g_p_i_o___p_r_t___type.html">GPIO_PRT_Type</a> *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a4cd08dbd4b55e3b80e34ed78694d1399">wcoOutPort</a></td></tr>
<tr class="memdesc:a4cd08dbd4b55e3b80e34ed78694d1399"><td class="mdescLeft">&#160;</td><td class="mdescRight">WCO Output port. <br /></td></tr>
<tr class="separator:a4cd08dbd4b55e3b80e34ed78694d1399"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a21df0ea373349c2365c3c71751faecdf"><td class="memItemLeft" align="right" valign="top"><a id="a21df0ea373349c2365c3c71751faecdf"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a21df0ea373349c2365c3c71751faecdf">wcoInPinNum</a></td></tr>
<tr class="memdesc:a21df0ea373349c2365c3c71751faecdf"><td class="mdescLeft">&#160;</td><td class="mdescRight">WCO Input pin. <br /></td></tr>
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<tr class="memitem:af05c29fe09183b5008bc639cca145628"><td class="memItemLeft" align="right" valign="top"><a id="af05c29fe09183b5008bc639cca145628"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#af05c29fe09183b5008bc639cca145628">wcoOutPinNum</a></td></tr>
<tr class="memdesc:af05c29fe09183b5008bc639cca145628"><td class="mdescLeft">&#160;</td><td class="mdescRight">WCO Output pin. <br /></td></tr>
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<tr class="memitem:a53675184c7b1eb602dc6a26bf94459af"><td class="memItemLeft" align="right" valign="top"><a id="a53675184c7b1eb602dc6a26bf94459af"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a53675184c7b1eb602dc6a26bf94459af">fllOutFreqHz</a></td></tr>
<tr class="memdesc:a53675184c7b1eb602dc6a26bf94459af"><td class="mdescLeft">&#160;</td><td class="mdescRight">FLL Output Frequency in Hz. <br /></td></tr>
<tr class="separator:a53675184c7b1eb602dc6a26bf94459af"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8a09ad0345b180d4a01c997d02be0d37"><td class="memItemLeft" align="right" valign="top"><a id="a8a09ad0345b180d4a01c997d02be0d37"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a8a09ad0345b180d4a01c997d02be0d37">fllMult</a></td></tr>
<tr class="memdesc:a8a09ad0345b180d4a01c997d02be0d37"><td class="mdescLeft">&#160;</td><td class="mdescRight">CLK_FLL_CONFIG register, FLL_MULT bits. <br /></td></tr>
<tr class="separator:a8a09ad0345b180d4a01c997d02be0d37"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a191c29dd33150eaf3d7453ddf3c4ec94"><td class="memItemLeft" align="right" valign="top"><a id="a191c29dd33150eaf3d7453ddf3c4ec94"></a>
uint16_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a191c29dd33150eaf3d7453ddf3c4ec94">fllRefDiv</a></td></tr>
<tr class="memdesc:a191c29dd33150eaf3d7453ddf3c4ec94"><td class="mdescLeft">&#160;</td><td class="mdescRight">CLK_FLL_CONFIG2 register, FLL_REF_DIV bits. <br /></td></tr>
<tr class="separator:a191c29dd33150eaf3d7453ddf3c4ec94"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0787b7b28041ad332ebc8f5579af9905"><td class="memItemLeft" align="right" valign="top"><a id="a0787b7b28041ad332ebc8f5579af9905"></a>
<a class="el" href="group__group__sysclk__fll__enums.html#gac8760ee841ca24255c9a4fee494b79aa">cy_en_fll_cco_ranges_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a0787b7b28041ad332ebc8f5579af9905">fllCcoRange</a></td></tr>
<tr class="memdesc:a0787b7b28041ad332ebc8f5579af9905"><td class="mdescLeft">&#160;</td><td class="mdescRight">CLK_FLL_CONFIG4 register, CCO_RANGE bits. <br /></td></tr>
<tr class="separator:a0787b7b28041ad332ebc8f5579af9905"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab2eb5c6da302f6d2f8ee682e88e422d9"><td class="memItemLeft" align="right" valign="top"><a id="ab2eb5c6da302f6d2f8ee682e88e422d9"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#ab2eb5c6da302f6d2f8ee682e88e422d9">enableOutputDiv</a></td></tr>
<tr class="memdesc:ab2eb5c6da302f6d2f8ee682e88e422d9"><td class="mdescLeft">&#160;</td><td class="mdescRight">CLK_FLL_CONFIG register, FLL_OUTPUT_DIV bit. <br /></td></tr>
<tr class="separator:ab2eb5c6da302f6d2f8ee682e88e422d9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a85bf3bd10fd6d5b6f61752429eb3a3e4"><td class="memItemLeft" align="right" valign="top"><a id="a85bf3bd10fd6d5b6f61752429eb3a3e4"></a>
uint16_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a85bf3bd10fd6d5b6f61752429eb3a3e4">lockTolerance</a></td></tr>
<tr class="memdesc:a85bf3bd10fd6d5b6f61752429eb3a3e4"><td class="mdescLeft">&#160;</td><td class="mdescRight">CLK_FLL_CONFIG2 register, LOCK_TOL bits. <br /></td></tr>
<tr class="separator:a85bf3bd10fd6d5b6f61752429eb3a3e4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a77d55142bb9dec0714fc64a93f6f4dbc"><td class="memItemLeft" align="right" valign="top"><a id="a77d55142bb9dec0714fc64a93f6f4dbc"></a>
uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a77d55142bb9dec0714fc64a93f6f4dbc">igain</a></td></tr>
<tr class="memdesc:a77d55142bb9dec0714fc64a93f6f4dbc"><td class="mdescLeft">&#160;</td><td class="mdescRight">CLK_FLL_CONFIG3 register, FLL_LF_IGAIN bits. <br /></td></tr>
<tr class="separator:a77d55142bb9dec0714fc64a93f6f4dbc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adb014eee199d17ff4fb9f3414090802a"><td class="memItemLeft" align="right" valign="top"><a id="adb014eee199d17ff4fb9f3414090802a"></a>
uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#adb014eee199d17ff4fb9f3414090802a">pgain</a></td></tr>
<tr class="memdesc:adb014eee199d17ff4fb9f3414090802a"><td class="mdescLeft">&#160;</td><td class="mdescRight">CLK_FLL_CONFIG3 register, FLL_LF_PGAIN bits. <br /></td></tr>
<tr class="separator:adb014eee199d17ff4fb9f3414090802a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae2ed1d86e659708c0fff7b6048f81d9d"><td class="memItemLeft" align="right" valign="top"><a id="ae2ed1d86e659708c0fff7b6048f81d9d"></a>
uint16_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#ae2ed1d86e659708c0fff7b6048f81d9d">settlingCount</a></td></tr>
<tr class="memdesc:ae2ed1d86e659708c0fff7b6048f81d9d"><td class="mdescLeft">&#160;</td><td class="mdescRight">CLK_FLL_CONFIG3 register, SETTLING_COUNT bits. <br /></td></tr>
<tr class="separator:ae2ed1d86e659708c0fff7b6048f81d9d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aebe424d7bbe9a21cced548331c77b67e"><td class="memItemLeft" align="right" valign="top"><a id="aebe424d7bbe9a21cced548331c77b67e"></a>
<a class="el" href="group__group__sysclk__fll__enums.html#ga777e08424e26c9cd8c2602b2114e716b">cy_en_fll_pll_output_mode_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#aebe424d7bbe9a21cced548331c77b67e">outputMode</a></td></tr>
<tr class="memdesc:aebe424d7bbe9a21cced548331c77b67e"><td class="mdescLeft">&#160;</td><td class="mdescRight">CLK_FLL_CONFIG3 register, BYPASS_SEL bits. <br /></td></tr>
<tr class="separator:aebe424d7bbe9a21cced548331c77b67e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a19a3aabadfc02a36b9afdfadc9d02503"><td class="memItemLeft" align="right" valign="top"><a id="a19a3aabadfc02a36b9afdfadc9d02503"></a>
uint16_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a19a3aabadfc02a36b9afdfadc9d02503">ccoFreq</a></td></tr>
<tr class="memdesc:a19a3aabadfc02a36b9afdfadc9d02503"><td class="mdescLeft">&#160;</td><td class="mdescRight">CLK_FLL_CONFIG4 register, CCO_FREQ bits. <br /></td></tr>
<tr class="separator:a19a3aabadfc02a36b9afdfadc9d02503"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a99297c1adc87330f617aee831dddee54"><td class="memItemLeft" align="right" valign="top"><a id="a99297c1adc87330f617aee831dddee54"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a99297c1adc87330f617aee831dddee54">pll0OutFreqHz</a></td></tr>
<tr class="memdesc:a99297c1adc87330f617aee831dddee54"><td class="mdescLeft">&#160;</td><td class="mdescRight">PLL0 output frequency in Hz. <br /></td></tr>
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<tr class="memitem:a0d8aeaad70d88c8f4baf071836a06275"><td class="memItemLeft" align="right" valign="top"><a id="a0d8aeaad70d88c8f4baf071836a06275"></a>
uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a0d8aeaad70d88c8f4baf071836a06275">pll0FeedbackDiv</a></td></tr>
<tr class="memdesc:a0d8aeaad70d88c8f4baf071836a06275"><td class="mdescLeft">&#160;</td><td class="mdescRight">PLL0 CLK_PLL_CONFIG register, FEEDBACK_DIV (P) bits. <br /></td></tr>
<tr class="separator:a0d8aeaad70d88c8f4baf071836a06275"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab727202809827d46f83babc6c682e76c"><td class="memItemLeft" align="right" valign="top"><a id="ab727202809827d46f83babc6c682e76c"></a>
uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#ab727202809827d46f83babc6c682e76c">pll0ReferenceDiv</a></td></tr>
<tr class="memdesc:ab727202809827d46f83babc6c682e76c"><td class="mdescLeft">&#160;</td><td class="mdescRight">PLL0 CLK_PLL_CONFIG register, REFERENCE_DIV (Q) bits. <br /></td></tr>
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<tr class="memitem:a680758675b8854de604d9d4fab7fefbe"><td class="memItemLeft" align="right" valign="top"><a id="a680758675b8854de604d9d4fab7fefbe"></a>
uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a680758675b8854de604d9d4fab7fefbe">pll0OutputDiv</a></td></tr>
<tr class="memdesc:a680758675b8854de604d9d4fab7fefbe"><td class="mdescLeft">&#160;</td><td class="mdescRight">PLL0 CLK_PLL_CONFIG register, OUTPUT_DIV bits. <br /></td></tr>
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<tr class="memitem:a9dd8eedd9675c59695b000681bd116a2"><td class="memItemLeft" align="right" valign="top"><a id="a9dd8eedd9675c59695b000681bd116a2"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a9dd8eedd9675c59695b000681bd116a2">pll0LfMode</a></td></tr>
<tr class="memdesc:a9dd8eedd9675c59695b000681bd116a2"><td class="mdescLeft">&#160;</td><td class="mdescRight">PLL0 CLK_PLL_CONFIG register, PLL_LF_MODE bit. <br /></td></tr>
<tr class="separator:a9dd8eedd9675c59695b000681bd116a2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5d227371da2d107e22447791b90603af"><td class="memItemLeft" align="right" valign="top"><a id="a5d227371da2d107e22447791b90603af"></a>
<a class="el" href="group__group__sysclk__fll__enums.html#ga777e08424e26c9cd8c2602b2114e716b">cy_en_fll_pll_output_mode_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a5d227371da2d107e22447791b90603af">pll0OutputMode</a></td></tr>
<tr class="memdesc:a5d227371da2d107e22447791b90603af"><td class="mdescLeft">&#160;</td><td class="mdescRight">PLL0 CLK_PLL_CONFIG register, BYPASS_SEL bits. <br /></td></tr>
<tr class="separator:a5d227371da2d107e22447791b90603af"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad4a6912689c1497e779b954f0881bd9d"><td class="memItemLeft" align="right" valign="top"><a id="ad4a6912689c1497e779b954f0881bd9d"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#ad4a6912689c1497e779b954f0881bd9d">pll1OutFreqHz</a></td></tr>
<tr class="memdesc:ad4a6912689c1497e779b954f0881bd9d"><td class="mdescLeft">&#160;</td><td class="mdescRight">PLL1 output frequency in Hz. <br /></td></tr>
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<tr class="memitem:a822c91d63bcd2196efbca8a917a73d3f"><td class="memItemLeft" align="right" valign="top"><a id="a822c91d63bcd2196efbca8a917a73d3f"></a>
uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a822c91d63bcd2196efbca8a917a73d3f">pll1FeedbackDiv</a></td></tr>
<tr class="memdesc:a822c91d63bcd2196efbca8a917a73d3f"><td class="mdescLeft">&#160;</td><td class="mdescRight">PLL1 CLK_PLL_CONFIG register, FEEDBACK_DIV (P) bits. <br /></td></tr>
<tr class="separator:a822c91d63bcd2196efbca8a917a73d3f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a149b197583cf6a74e364550ba48c6693"><td class="memItemLeft" align="right" valign="top"><a id="a149b197583cf6a74e364550ba48c6693"></a>
uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a149b197583cf6a74e364550ba48c6693">pll1ReferenceDiv</a></td></tr>
<tr class="memdesc:a149b197583cf6a74e364550ba48c6693"><td class="mdescLeft">&#160;</td><td class="mdescRight">PLL1 CLK_PLL_CONFIG register, REFERENCE_DIV (Q) bits. <br /></td></tr>
<tr class="separator:a149b197583cf6a74e364550ba48c6693"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af22db59686e2e4bec9d96fa5ea71c9e1"><td class="memItemLeft" align="right" valign="top"><a id="af22db59686e2e4bec9d96fa5ea71c9e1"></a>
uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#af22db59686e2e4bec9d96fa5ea71c9e1">pll1OutputDiv</a></td></tr>
<tr class="memdesc:af22db59686e2e4bec9d96fa5ea71c9e1"><td class="mdescLeft">&#160;</td><td class="mdescRight">PLL1 CLK_PLL_CONFIG register, OUTPUT_DIV bits. <br /></td></tr>
<tr class="separator:af22db59686e2e4bec9d96fa5ea71c9e1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5dcb0598314abb9b7950c48284c59caf"><td class="memItemLeft" align="right" valign="top"><a id="a5dcb0598314abb9b7950c48284c59caf"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a5dcb0598314abb9b7950c48284c59caf">pll1LfMode</a></td></tr>
<tr class="memdesc:a5dcb0598314abb9b7950c48284c59caf"><td class="mdescLeft">&#160;</td><td class="mdescRight">PLL1 CLK_PLL_CONFIG register, PLL_LF_MODE bit. <br /></td></tr>
<tr class="separator:a5dcb0598314abb9b7950c48284c59caf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afce3b2193781d11be4504c745e4bf4d4"><td class="memItemLeft" align="right" valign="top"><a id="afce3b2193781d11be4504c745e4bf4d4"></a>
<a class="el" href="group__group__sysclk__fll__enums.html#ga777e08424e26c9cd8c2602b2114e716b">cy_en_fll_pll_output_mode_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#afce3b2193781d11be4504c745e4bf4d4">pll1OutputMode</a></td></tr>
<tr class="memdesc:afce3b2193781d11be4504c745e4bf4d4"><td class="mdescLeft">&#160;</td><td class="mdescRight">PLL1 CLK_PLL_CONFIG register, BYPASS_SEL bits. <br /></td></tr>
<tr class="separator:afce3b2193781d11be4504c745e4bf4d4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a787f9997208f735c9a01355d2afb66f9"><td class="memItemLeft" align="right" valign="top"><a id="a787f9997208f735c9a01355d2afb66f9"></a>
<a class="el" href="group__group__sysclk__path__src__enums.html#ga8ddaf9023a02dee0d1f9a5629d6ccfe6">cy_en_clkpath_in_sources_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a787f9997208f735c9a01355d2afb66f9">path0Src</a></td></tr>
<tr class="memdesc:a787f9997208f735c9a01355d2afb66f9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Input multiplexer0 clock source. <br /></td></tr>
<tr class="separator:a787f9997208f735c9a01355d2afb66f9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9dfb6a6fb71573fabb0206c0ebe07cea"><td class="memItemLeft" align="right" valign="top"><a id="a9dfb6a6fb71573fabb0206c0ebe07cea"></a>
<a class="el" href="group__group__sysclk__path__src__enums.html#ga8ddaf9023a02dee0d1f9a5629d6ccfe6">cy_en_clkpath_in_sources_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a9dfb6a6fb71573fabb0206c0ebe07cea">path1Src</a></td></tr>
<tr class="memdesc:a9dfb6a6fb71573fabb0206c0ebe07cea"><td class="mdescLeft">&#160;</td><td class="mdescRight">Input multiplexer1 clock source. <br /></td></tr>
<tr class="separator:a9dfb6a6fb71573fabb0206c0ebe07cea"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a93a8d503643849cba8702ca5e419792a"><td class="memItemLeft" align="right" valign="top"><a id="a93a8d503643849cba8702ca5e419792a"></a>
<a class="el" href="group__group__sysclk__path__src__enums.html#ga8ddaf9023a02dee0d1f9a5629d6ccfe6">cy_en_clkpath_in_sources_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a93a8d503643849cba8702ca5e419792a">path2Src</a></td></tr>
<tr class="memdesc:a93a8d503643849cba8702ca5e419792a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Input multiplexer2 clock source. <br /></td></tr>
<tr class="separator:a93a8d503643849cba8702ca5e419792a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9389baf5842464fe02e34ce1743d56ea"><td class="memItemLeft" align="right" valign="top"><a id="a9389baf5842464fe02e34ce1743d56ea"></a>
<a class="el" href="group__group__sysclk__path__src__enums.html#ga8ddaf9023a02dee0d1f9a5629d6ccfe6">cy_en_clkpath_in_sources_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a9389baf5842464fe02e34ce1743d56ea">path3Src</a></td></tr>
<tr class="memdesc:a9389baf5842464fe02e34ce1743d56ea"><td class="mdescLeft">&#160;</td><td class="mdescRight">Input multiplexer3 clock source. <br /></td></tr>
<tr class="separator:a9389baf5842464fe02e34ce1743d56ea"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7b37fc27684c44cb73a6e735f2ed3e85"><td class="memItemLeft" align="right" valign="top"><a id="a7b37fc27684c44cb73a6e735f2ed3e85"></a>
<a class="el" href="group__group__sysclk__path__src__enums.html#ga8ddaf9023a02dee0d1f9a5629d6ccfe6">cy_en_clkpath_in_sources_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a7b37fc27684c44cb73a6e735f2ed3e85">path4Src</a></td></tr>
<tr class="memdesc:a7b37fc27684c44cb73a6e735f2ed3e85"><td class="mdescLeft">&#160;</td><td class="mdescRight">Input multiplexer4 clock source. <br /></td></tr>
<tr class="separator:a7b37fc27684c44cb73a6e735f2ed3e85"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac8960ec7f869ecde228e0b01223f69f2"><td class="memItemLeft" align="right" valign="top"><a id="ac8960ec7f869ecde228e0b01223f69f2"></a>
<a class="el" href="group__group__sysclk__path__src__enums.html#ga8ddaf9023a02dee0d1f9a5629d6ccfe6">cy_en_clkpath_in_sources_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#ac8960ec7f869ecde228e0b01223f69f2">path5Src</a></td></tr>
<tr class="memdesc:ac8960ec7f869ecde228e0b01223f69f2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Input multiplexer5 clock source. <br /></td></tr>
<tr class="separator:ac8960ec7f869ecde228e0b01223f69f2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a562c534fa54842884237d704cad64ac8"><td class="memItemLeft" align="right" valign="top">uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a562c534fa54842884237d704cad64ac8">clkFastDiv</a></td></tr>
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<a class="el" href="group__group__systick__data__structures.html#ga466b1e8fe4278011eab77a691ce2b8f9">cy_en_systick_clock_source_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a40f254fcafbef0edae68494021322d62">clkSrcAltSysTick</a></td></tr>
<tr class="memdesc:a40f254fcafbef0edae68494021322d62"><td class="mdescLeft">&#160;</td><td class="mdescRight">SysTick Source. <br /></td></tr>
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uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#af03bdcd914aaa17fc530c9c1264e46f7">altHFcLoad</a></td></tr>
<tr class="memdesc:af03bdcd914aaa17fc530c9c1264e46f7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Load Cap (pF) <br /></td></tr>
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uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a55ae459ce519c5b5124429ef7625ef73">altHFxtalStartUpTime</a></td></tr>
<tr class="memdesc:a55ae459ce519c5b5124429ef7625ef73"><td class="mdescLeft">&#160;</td><td class="mdescRight">Startup Time (us) <br /></td></tr>
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<tr class="memitem:a6dd0cc3cdc69074a75f9335ca3a5ff70"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a6dd0cc3cdc69074a75f9335ca3a5ff70">altHFclkFreq</a></td></tr>
<tr class="memdesc:a6dd0cc3cdc69074a75f9335ca3a5ff70"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clock Frequency.  <a href="#a6dd0cc3cdc69074a75f9335ca3a5ff70">More...</a><br /></td></tr>
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uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#a70301630eba570879b56a0859b4deda8">altHFsysClkDiv</a></td></tr>
<tr class="memdesc:a70301630eba570879b56a0859b4deda8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clock Divider. <br /></td></tr>
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uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pra__system__config__t.html#aa1c196041d52fee999ec0a239d92388c">altHFvoltageReg</a></td></tr>
<tr class="memdesc:aa1c196041d52fee999ec0a239d92388c"><td class="mdescLeft">&#160;</td><td class="mdescRight">BLE Voltage Regulator. <br /></td></tr>
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<h2 class="groupheader">Field Documentation</h2>
<a id="a562c534fa54842884237d704cad64ac8"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a562c534fa54842884237d704cad64ac8">&#9670;&nbsp;</a></span>clkFastDiv</h2>

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          <td class="memname">uint8_t cy_stc_pra_system_config_t::clkFastDiv</td>
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<p>Fast clock divider. </p>
<p>User has to pass actual divider-1 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#afb870af1bd9949f57e24b4399ea329c1">&#9670;&nbsp;</a></span>clkPeriDiv</h2>

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          <td class="memname">uint8_t cy_stc_pra_system_config_t::clkPeriDiv</td>
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<p>Peri clock divider. </p>
<p>User has to pass actual divider-1 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a7d2c76cc194da3c5d6bbd06f988882ba">&#9670;&nbsp;</a></span>clkSlowDiv</h2>

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          <td class="memname">uint8_t cy_stc_pra_system_config_t::clkSlowDiv</td>
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<p>Slow clock divider. </p>
<p>User has to pass actual divider-1 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a6dd0cc3cdc69074a75f9335ca3a5ff70">&#9670;&nbsp;</a></span>altHFclkFreq</h2>

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          <td class="memname">uint32_t cy_stc_pra_system_config_t::altHFclkFreq</td>
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<p>Clock Frequency. </p>
<p>0 -&gt; 16MHz and 1 -&gt; 32MHz. Any other value except 0 and 1 is invalid </p>

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